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? Configurable number of data bits, 4-16 (plus the parity bit, if enabled)
? HW parity bit generation and check
? Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2
? HW collision detection
? Multi-processor mode
? IrDA modulator on USART0
? SmartCard (ISO7816) mode
? Separate interrupt vectors for receive and transmit interrupts
? Loopback mode
? Half duplex communication
? Communication debugging
16.3 Functional Description
An overview of the USART module is shown in Figure 16.1 (p. 178) .
Figure 16.1. USART Overview
Peripheral Bus
USn_CS
U(S)n_TX
UART Control
and status
IrDA
TX Buffer
(2-level FIFO)
TX Shift Register
RX Buffer
(2-level FIFO)
! RXBLOCK
RX Shift Register
m odulator
USn_CLK
Pin
ctrl
Baud rate
generator
U(S)n_RX
IrDA
dem odulator
16.3.1 Modes of Operation
The USART operates in either asynchronous or synchronous mode.
In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated
by the bus master, and both the master and slave sample and transmit data according to this clock.
Both master and slave modes are supported by the USART. The synchronous communication mode is
compatible with the Serial Peripheral Interface Bus (SPI) standard.
In asynchronous mode, no separate clock signal is transmitted with the data on the bus. The USART
receiver thus has to determine where to sample the data on the bus from the actual data. To make this
possible, additional synchronization bits are added to the data when operating in asynchronous mode,
resulting in a slight overhead.
2011-04-12 - d0001_Rev1.10
178
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